摘要
s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure reduces the propagation delay and has higher operating speed.Based on this structure,an im proved D- flip- flop(DFF) using dynam ic circuit technique is proposed.A prototype is fabricated and the measured results show that this prescaler works well in gigahertz frequency range and consumes only35 m W(including three power- hungry output buffers) when the input frequency is2 .5 GHz and the power supply voltage is2 .5 V.Due to its excellent perform ance,the prescaler could be applied to many RF system s.
提出了一种应用新的电路结构和动态电路技术的双模预分频器 ,它已用 0 .2 5μm CMOS数字工艺实现 .新的优化结构减少了电路的传输延迟 ,提高了电路速度 .基于这种优化结构和动态电路技术 ,提出了改进的 D型触发器 .为了验证其功能 ,制作了一个试验型芯片 .经测试 ,该分频器在可以工作于 GHz频率范围 ;在电源电压为 2 .5 V ,输入频率为 2 .5 GHz时 ,其功耗仅为 35 m W(包括三个功耗很大的输出缓冲器的功耗 ) .由于其具有良好的性能 ,该分频器可应用于许多射频系统中 .
基金
国家自然科学基金资助项目 (批准号 :6 96 36 0 30 )~~
