Aggregation is an important and commonplace operation in wireless sensor networks. Due to wireless interferences aggregation in wireless sensor networks often suffers from packet collisions. In order to solve the coll...Aggregation is an important and commonplace operation in wireless sensor networks. Due to wireless interferences aggregation in wireless sensor networks often suffers from packet collisions. In order to solve the collision problem aggregation scheduling is extensively researched in recent years. In many sensor network applications such as real-time monitoring, aggregation time is the most concerned performance. This paper considers the minimum-time aggregation scheduling problem in duty-cycled wireless sensor networks for the first time. We show that this problem is NP-hard and present an approximation algorithm based on connected dominating set. The theoretical analysis shows that the proposed algorithm is a nearly-constant approximation. Simulation shows that the scheduling algorithm has a good performance.展开更多
A rally integrated receiver RF front-end that meets WCDMA/GSM system requirements is presented.It supports SAW-less operation for WCDMA.To improve the linearity in terms of both IP3 and IP2,the RF front-end is compris...A rally integrated receiver RF front-end that meets WCDMA/GSM system requirements is presented.It supports SAW-less operation for WCDMA.To improve the linearity in terms of both IP3 and IP2,the RF front-end is comprised of multiple-gated LNAs with capacitive desensitization,current-mode passive mixers with the proposed IP2 calibration circuit and reconfigurable Tow-Thomas-like biquad TIAs.A new power-saving multi-mode divider with low phase noise is proposed to provide the 4-phase 25%-duty-cycle LO.In addition,a constant-g_m biasing with an on-chip resistor is adopted to make the conversion gain invulnerable to the process and temperature variations of the transimpedance.This RF front-end is integrated in a receiver with an on-chip frequency synthesizer in 0.13μm CMOS.The measurement results show that owing to this high-linearity RF front-end,the receiver achieves -6 dBm IIP3 and better than ＋60 dBm IIP2 for all modes and bands.展开更多
A great amount of work addressed methods for predicting the battery lifetime in wireless sensor systems. In spite of these efforts, the reported experimental results demonstrate that the duty-cycle current average met...A great amount of work addressed methods for predicting the battery lifetime in wireless sensor systems. In spite of these efforts, the reported experimental results demonstrate that the duty-cycle current average method, which is widely used to this aim, fails in accurately estimating the battery life time of most of the presented wireless sensor system applications. The aim of this paper is to experimentally assess the duty-cycle current average method in order to give more effective insight on the effectiveness of the method. An electronic metering system, based on a dedicated PCB, has been designed and developed to experimentally measure node current consumption profiles and charge extracted from the battery in two selected case studies. A battery lifetime measurement (during 30 days) has been carried out. Experimental results have been assessed and compared with estimations given by using the duty-cycle current average method. Based on the measurement results, we show that the assumptions on which the method is based do not hold in real operating cases. The rationality of the duty-cycle current average method needs reconsidering.展开更多
Energy minimization is an important goal in wireless implanted communication devices. In this context, a cross-layer method is used to optimize parameters in different layers of OSI model, but, there are still several...Energy minimization is an important goal in wireless implanted communication devices. In this context, a cross-layer method is used to optimize parameters in different layers of OSI model, but, there are still several challenges affecting the optimization algorithm. The first point is the accurate energy model, and the second point is the suitable channel model exclude traditional free space channel model. In this paper, we establish a system level accurate energy consumption model and build a suitable channel model for implanted communication devices;analysis the energy-constrained duty cycle optimization with a cross-layer method. Simulation results reveal that adaptive duty cycle to minimize the energy consumption of the wireless implanted communication system is implemented based on accurate energy consumption model and channel model. Simulation results show a good performance on energy saving.展开更多
The resistance torque of a piston stage II com- pressor generates strenuous fluctuations in a rotational period, and this can lead to negative influences on the working performance of the compressor. To restrain the s...The resistance torque of a piston stage II com- pressor generates strenuous fluctuations in a rotational period, and this can lead to negative influences on the working performance of the compressor. To restrain the strenuous fluctuations in the piston stage II compressor, a variable duty-cycle control method based on the resistance torque is proposed. A dynamic model of a stage II com- pressor is set up, and the resistance torque and other characteristic parameters are acquired as the control tar- gets. Then, a variable duty-cycle control method is applied to track the resistance torque, thereby improving the working performance of the compressor. Simulated results show that the compressor, driven by the proposed method, requires lower current, while the rotating speed and the output torque remain comparable to the traditional vari- able-frequency control methods. A variable duty-cycle control system is developed, and the experimental results prove that the proposed method can help reduce the specific power, input power, and working noise of the compressor to 0.97 kW.m-3.min-1, 0.09 kW and 3.10 dB, respectively, under the same conditions of discharge pressure of 2.00 MPa and a discharge volume of 0.095 m3/rain. The proposed variable duty-cycle control method tracks the resistance torque dynamically, and improves the working performance of a Stage II Compressor. The pro- posed variable duty-cycle control method can be applied to other compressors, and can provide theoretical guidance for the compressor.展开更多
Phase-locked loops (PLLs) are essential wherever a local event is synchronized with a periodic external event. They are utilized as on-chip clock frequency generators to synthesize a low skew and higher internal frequ...Phase-locked loops (PLLs) are essential wherever a local event is synchronized with a periodic external event. They are utilized as on-chip clock frequency generators to synthesize a low skew and higher internal frequency clock from an external lower frequency signal and its characterization and measurement have recently been calling for more and more attention. In this paper, a built-in on-chip circuit for measuring jitter of PLL based on a duty cycle modulation vernier delay line is proposed and demonstrated. The circuit employs two delay lines to measure the timing difference and transform the difference signal into digital words. The vernier lines are composed of delay cells whose duty cycle can be adjusted by a feedback voltage. It enables the circuit to have a self calibration capability which eliminates the mismatch problem caused by the process variation.展开更多
基金supported by the Key Project of National Natural Science Foundation of China under Grant No.61033015the National Natural Science Foundation of China/Research Grants Council of Hong Kong Joint Research Scheme under Grant No.60831160525,and the National Natural Science Foundation of China under Grant No.60933001
文摘Aggregation is an important and commonplace operation in wireless sensor networks. Due to wireless interferences aggregation in wireless sensor networks often suffers from packet collisions. In order to solve the collision problem aggregation scheduling is extensively researched in recent years. In many sensor network applications such as real-time monitoring, aggregation time is the most concerned performance. This paper considers the minimum-time aggregation scheduling problem in duty-cycled wireless sensor networks for the first time. We show that this problem is NP-hard and present an approximation algorithm based on connected dominating set. The theoretical analysis shows that the proposed algorithm is a nearly-constant approximation. Simulation shows that the scheduling algorithm has a good performance.
基金supported by the National Science and Technology Major Project of China(No.2009ZX01031-003-002)the National High Technology Research and Development Program of China(No.2009AA011605)
文摘A rally integrated receiver RF front-end that meets WCDMA/GSM system requirements is presented.It supports SAW-less operation for WCDMA.To improve the linearity in terms of both IP3 and IP2,the RF front-end is comprised of multiple-gated LNAs with capacitive desensitization,current-mode passive mixers with the proposed IP2 calibration circuit and reconfigurable Tow-Thomas-like biquad TIAs.A new power-saving multi-mode divider with low phase noise is proposed to provide the 4-phase 25%-duty-cycle LO.In addition,a constant-g_m biasing with an on-chip resistor is adopted to make the conversion gain invulnerable to the process and temperature variations of the transimpedance.This RF front-end is integrated in a receiver with an on-chip frequency synthesizer in 0.13μm CMOS.The measurement results show that owing to this high-linearity RF front-end,the receiver achieves -6 dBm IIP3 and better than ＋60 dBm IIP2 for all modes and bands.
文摘A great amount of work addressed methods for predicting the battery lifetime in wireless sensor systems. In spite of these efforts, the reported experimental results demonstrate that the duty-cycle current average method, which is widely used to this aim, fails in accurately estimating the battery life time of most of the presented wireless sensor system applications. The aim of this paper is to experimentally assess the duty-cycle current average method in order to give more effective insight on the effectiveness of the method. An electronic metering system, based on a dedicated PCB, has been designed and developed to experimentally measure node current consumption profiles and charge extracted from the battery in two selected case studies. A battery lifetime measurement (during 30 days) has been carried out. Experimental results have been assessed and compared with estimations given by using the duty-cycle current average method. Based on the measurement results, we show that the assumptions on which the method is based do not hold in real operating cases. The rationality of the duty-cycle current average method needs reconsidering.
文摘Energy minimization is an important goal in wireless implanted communication devices. In this context, a cross-layer method is used to optimize parameters in different layers of OSI model, but, there are still several challenges affecting the optimization algorithm. The first point is the accurate energy model, and the second point is the suitable channel model exclude traditional free space channel model. In this paper, we establish a system level accurate energy consumption model and build a suitable channel model for implanted communication devices;analysis the energy-constrained duty cycle optimization with a cross-layer method. Simulation results reveal that adaptive duty cycle to minimize the energy consumption of the wireless implanted communication system is implemented based on accurate energy consumption model and channel model. Simulation results show a good performance on energy saving.
基金Supported by National Natural Science Foundation of China(Grant No.51275452)Zhejiang Provincical Natural Science Foundation of China(Grant No.LY14E050021)Commonweal Technology Project of Science and Technology Department of Zhejiang Province,China(Grant No.2015C31071)
文摘The resistance torque of a piston stage II com- pressor generates strenuous fluctuations in a rotational period, and this can lead to negative influences on the working performance of the compressor. To restrain the strenuous fluctuations in the piston stage II compressor, a variable duty-cycle control method based on the resistance torque is proposed. A dynamic model of a stage II com- pressor is set up, and the resistance torque and other characteristic parameters are acquired as the control tar- gets. Then, a variable duty-cycle control method is applied to track the resistance torque, thereby improving the working performance of the compressor. Simulated results show that the compressor, driven by the proposed method, requires lower current, while the rotating speed and the output torque remain comparable to the traditional vari- able-frequency control methods. A variable duty-cycle control system is developed, and the experimental results prove that the proposed method can help reduce the specific power, input power, and working noise of the compressor to 0.97 kW.m-3.min-1, 0.09 kW and 3.10 dB, respectively, under the same conditions of discharge pressure of 2.00 MPa and a discharge volume of 0.095 m3/rain. The proposed variable duty-cycle control method tracks the resistance torque dynamically, and improves the working performance of a Stage II Compressor. The pro- posed variable duty-cycle control method can be applied to other compressors, and can provide theoretical guidance for the compressor.
文摘Phase-locked loops (PLLs) are essential wherever a local event is synchronized with a periodic external event. They are utilized as on-chip clock frequency generators to synthesize a low skew and higher internal frequency clock from an external lower frequency signal and its characterization and measurement have recently been calling for more and more attention. In this paper, a built-in on-chip circuit for measuring jitter of PLL based on a duty cycle modulation vernier delay line is proposed and demonstrated. The circuit employs two delay lines to measure the timing difference and transform the difference signal into digital words. The vernier lines are composed of delay cells whose duty cycle can be adjusted by a feedback voltage. It enables the circuit to have a self calibration capability which eliminates the mismatch problem caused by the process variation.
