With the growing popularity of data-intensive services on the Internet, the traditional process-centric model for business process meets challenges due to the lack of abilities to describe data semantics and dependenc...With the growing popularity of data-intensive services on the Internet, the traditional process-centric model for business process meets challenges due to the lack of abilities to describe data semantics and dependencies, resulting in the inflexibility of the design and implement for the processes. This paper proposes a novel data-aware business process model which is able to describe both explicit control flow and implicit data flow. Data model with dependencies which are formulated by Linear-time Temporal Logic(LTL) is presented, and their satisfiability is validated by an automaton-based model checking algorithm. Data dependencies are fully considered in modeling phase, which helps to improve the efficiency and reliability of programming during developing phase. Finally, a prototype system based on j BPM for data-aware workflow is designed using such model, and has been deployed to Beijing Kingfore heating management system to validate the flexibility, efficacy and convenience of our approach for massive coding and large-scale system management in reality.展开更多
针对社交媒体数据感知成本高、数据感知效率低等问题,提出了社交媒体嵌入关系多阶段数据感知方法（online social media-multi stage data aware,OSM-MSDA）。该方法以数据感知对象内部关系的分布特征为基础,构造一个具有偏好特征的种...针对社交媒体数据感知成本高、数据感知效率低等问题,提出了社交媒体嵌入关系多阶段数据感知方法（online social media-multi stage data aware,OSM-MSDA）。该方法以数据感知对象内部关系的分布特征为基础,构造一个具有偏好特征的种子网络;采用Metropolis-Hastings方法优先选取数据感知对象中高度节点的邻接关系,快速填充特征网络,实现网络轮廓探测;使用基于马尔可夫生灭机制的延迟拒绝方法控制概率转移核,对局部耦合关系进行修剪,确保连通关系疏密的合理分布。实验结果表明：OSM-MSDA建立的多阶段渐进数据抽样方法,能够克服已有数据感知方法采集样本的盲目性,在宏观尺度准确、高效的感知社交媒体嵌入关系的社会资本特征,确保特征网络与数据感知对象的结构更具有一致性,同时还能降低数据的使用成本,将数据处理效率提高32%~63%。展开更多
This paper represents current research in low-power Very Large Scale Integration (VLSI) domain. Nowadays low power has become more sought research topic in electronic industry. Power dissipation is the most important ...This paper represents current research in low-power Very Large Scale Integration (VLSI) domain. Nowadays low power has become more sought research topic in electronic industry. Power dissipation is the most important area while designing the VLSI chip. Today almost all of the high speed switching devices include the Ternary Content Addressable Memory (TCAM) as one of the most important features. When a device consumes less power that becomes reliable and it would work with more efficiency. Complementary Metal Oxide Semiconductor (CMOS) technology is best known for low power consumption devices. This paper aims at designing a router application device which consumes less power and works more efficiently. Various strategies, methodologies and power management techniques for low power circuits and systems are discussed in this research. From this research the challenges could be developed that might be met while designing low power high performance circuit. This work aims at developing Data Aware AND-type match line architecture for TCAM. A TCAM macro of 256 × 128 was designed using Cadence Advanced Development Environment (ADE) with 90 nm technology file from Taiwan Semiconductor Manufacturing Company (TSMC). The result shows that the proposed Data Aware architecture provides around 35% speed and 45% power improvement over existing architecture.展开更多
基金supported by the National Natural Science Foundation of China (No. 61502043, No. 61132001)Beijing Natural Science Foundation (No. 4162042)BeiJing Talents Fund (No. 2015000020124G082)
文摘With the growing popularity of data-intensive services on the Internet, the traditional process-centric model for business process meets challenges due to the lack of abilities to describe data semantics and dependencies, resulting in the inflexibility of the design and implement for the processes. This paper proposes a novel data-aware business process model which is able to describe both explicit control flow and implicit data flow. Data model with dependencies which are formulated by Linear-time Temporal Logic(LTL) is presented, and their satisfiability is validated by an automaton-based model checking algorithm. Data dependencies are fully considered in modeling phase, which helps to improve the efficiency and reliability of programming during developing phase. Finally, a prototype system based on j BPM for data-aware workflow is designed using such model, and has been deployed to Beijing Kingfore heating management system to validate the flexibility, efficacy and convenience of our approach for massive coding and large-scale system management in reality.
文摘针对社交媒体数据感知成本高、数据感知效率低等问题,提出了社交媒体嵌入关系多阶段数据感知方法（online social media-multi stage data aware,OSM-MSDA）。该方法以数据感知对象内部关系的分布特征为基础,构造一个具有偏好特征的种子网络;采用Metropolis-Hastings方法优先选取数据感知对象中高度节点的邻接关系,快速填充特征网络,实现网络轮廓探测;使用基于马尔可夫生灭机制的延迟拒绝方法控制概率转移核,对局部耦合关系进行修剪,确保连通关系疏密的合理分布。实验结果表明：OSM-MSDA建立的多阶段渐进数据抽样方法,能够克服已有数据感知方法采集样本的盲目性,在宏观尺度准确、高效的感知社交媒体嵌入关系的社会资本特征,确保特征网络与数据感知对象的结构更具有一致性,同时还能降低数据的使用成本,将数据处理效率提高32%~63%。
文摘This paper represents current research in low-power Very Large Scale Integration (VLSI) domain. Nowadays low power has become more sought research topic in electronic industry. Power dissipation is the most important area while designing the VLSI chip. Today almost all of the high speed switching devices include the Ternary Content Addressable Memory (TCAM) as one of the most important features. When a device consumes less power that becomes reliable and it would work with more efficiency. Complementary Metal Oxide Semiconductor (CMOS) technology is best known for low power consumption devices. This paper aims at designing a router application device which consumes less power and works more efficiently. Various strategies, methodologies and power management techniques for low power circuits and systems are discussed in this research. From this research the challenges could be developed that might be met while designing low power high performance circuit. This work aims at developing Data Aware AND-type match line architecture for TCAM. A TCAM macro of 256 × 128 was designed using Cadence Advanced Development Environment (ADE) with 90 nm technology file from Taiwan Semiconductor Manufacturing Company (TSMC). The result shows that the proposed Data Aware architecture provides around 35% speed and 45% power improvement over existing architecture.
