摘要
针对传统Data-aware结构SRAM读操作过程中出现的行半选择带来的功耗浪费问题,提出了一种改进型data-aware 9T结构的SRAM电路.与传统SRAM相比,该结构通过Cross-Point读的访问方式解决了读过程中被选中行中,由于半选择单元存在读通路引起的位线功耗浪费问题.实验数据表明,提出的SRAM电路,至多可以降低514%位线上消耗的功耗.测试电路采用0.13μm工艺,设计了一个16kb SRAM电路,工作电压为420mV,平均功耗为5.37μW.
Conventional Data-aware structure SRAM has power waste issue in read process due to row half-select, thus this paper proposes an improved 9T SRAM.Compared with traditional SRAM,the proposed scheme solves the power problem caused by the read path of half-selected cells in the selected row.The simulation result proves that the proposed scheme can reduce power dissipation on bitline by 5 14% at most.A 1 6kb SRAM test scheme is implemented in 0.13μm technology operating at 0.42V,with with measured power consumption of 5.37μW.
出处
《微电子学与计算机》
CSCD
北大核心
2015年第9期28-32,共5页
Microelectronics & Computer
关键词
亚阈值
低功耗
SRAM
data-aware
SRAM
data-aware
subthreshold
low power
