We demonstrate that the insertion of a graphene tunnel barrier between Heusler alloy Co_2MnSi and the germanium（Ge） channel modulates the Schottky barrier height and the resistance–area product of the spin diode. W...We demonstrate that the insertion of a graphene tunnel barrier between Heusler alloy Co_2MnSi and the germanium（Ge） channel modulates the Schottky barrier height and the resistance–area product of the spin diode. We confirm that the Fermi level is depinned and a reduction in the electron Schottky barrier height（SBH） occurs following the insertion of the graphene layer between Co_2MnSi and Ge. The electron SBH is modulated in the 0.34 eV–0.61 eV range. Furthermore,the transport mechanism changes from rectifying to symmetric tunneling following the insertion. This behavior provides a pathway for highly efficient spin injection from a Heusler alloy into a Ge channel with high electron and hole mobility.展开更多
Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire inpu...Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant No.61504107)the Fundamental Research Funds for the Central Universities,China(Grant Nos.3102014JCQ01059 and 3102015ZY043)
文摘We demonstrate that the insertion of a graphene tunnel barrier between Heusler alloy Co_2MnSi and the germanium（Ge） channel modulates the Schottky barrier height and the resistance–area product of the spin diode. We confirm that the Fermi level is depinned and a reduction in the electron Schottky barrier height（SBH） occurs following the insertion of the graphene layer between Co_2MnSi and Ge. The electron SBH is modulated in the 0.34 eV–0.61 eV range. Furthermore,the transport mechanism changes from rectifying to symmetric tunneling following the insertion. This behavior provides a pathway for highly efficient spin injection from a Heusler alloy into a Ge channel with high electron and hole mobility.
基金Project supported by the National Science and Technology Major Projects of China(No.2012ZX03001018-001)the Fundamental Research Funds for the Central Universities,China(No.K50511250006)
文摘Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.
