摘要
提出一个使用VHDL语言建立的32位浮点DSPs的外设模型,并分析外设的结构,各部分的工作原理以及相互之间的通信.外设模型中包括了DMA、程序存储器控制器(PMC)、数据存储器控制器(DMC)、外部存储器接口(EMIF)、外设总线控制器(PBC)和定时器,中断选择以及启动逻辑等.模型具有单周期数据存取,多条指令并行读取,程序存储器的高速cache策略,DMA四通道独立控制与操作,DMA以及CPU的两个数据通道可以同时访问数据存储空间等特点.
A 32 bit floating-point digital signal processor peripherals module constructed by VHDL is proposed. Its internal structure and each block's operation process is discussed in detail. The module includes the following peripheral blocks viz.: DMA, data memory controller, program memory controller, external memory interface, peripherals bus controller, timer, interrupt selector and boot logic. It has many characteristics such as single-clock-access; multi-instructions parallel loading; high-speed cache strategy; four independent channels in DMA, etc.
出处
《北京理工大学学报》
EI
CAS
CSCD
北大核心
2004年第5期431-434,共4页
Transactions of Beijing Institute of Technology
基金
国家部委预研项目(200205)
