摘要
介绍了VHDL逻辑级模拟系统中模拟模块的设计和实现。模拟模块引入一种改进后的事件驱动模拟算法,该事件驱动模拟算法采用时间列表和信号列表双重检索的组织结构,能够显著减少检索事件的时间,并在计算元件负载和模拟周期推进等方面进行了优化。实验结果表明,模拟系统能正确、高效地对VHDL电路模型进行模拟。
This paper presents design and implementation of the simulation module in a logic-level VHDL simulation system. The simulation module introduces a improved event-driven simulation algorithm which greatly reduces the time of finding events by adopting a dual-search structure with time list and signal list, and optimizes phases of evaluating load components and the process of advancing simulation cycles. Results of experiments verify the validity and efficiency of the simulation system simulating circuit models described by VHDL.
出处
《微电子学与计算机》
CSCD
北大核心
2004年第3期106-108,共3页
Microelectronics & Computer
基金
上海市应用材料研究与发展基金资助项目(0215)
