摘要
随着大规模集成电路的复杂性日益增加,逻辑模拟开始采用并行离散事件模拟技术。在现有的基于时间偏差协议的并行逻辑模拟系统的基础上,提出了一个动态负载平衡模型,模型能够针对模拟时的负载变化,进行以一组模拟对象为单位的迁移以实现负载平衡。提出模拟推进度的概念,作为对并行逻辑模拟过程中的负载进行准确的衡量标准。
With the rapid growth of complexity of VLSI, more and more logic simulation has adopted parallel discrete event simulation. On the basis of a time warp based parallel logic simulation system, a model of dynamic load balancing is presented. The model can migrate load by a group of simulation objects withthe change of the load. A new concept called simulation advance progress is introduced, which can be a accurate metrics for the load.
出处
《计算机工程与设计》
CSCD
北大核心
2005年第6期1463-1465,共3页
Computer Engineering and Design
基金
上海应用材料研究发展基金项目(0215)
关键词
时间偏差协议
并行逻辑模拟
动态负载平衡
模拟推进度
time warp protocol
parallel logic simulation
dynamic load balancing
simulation advance progress
