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New Generation Processor Architecture Research 被引量:1

New Generation Processor Architecture Research
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摘要 With the rapid development of microelectronics and hardware,the use of ever faster micro processors and new architecture must be continued to meet tomorrow′s computing needs. New processor microarchitectures are needed to push performance further and to use higher transistor counts effectively.At the same time,aiming at different usages,the processor has been optimized in different aspects,such as high performace,low power consumption,small chip area and high security. SOC (System on chip)and SCMP (Single Chip Multi Processor) constitute the main processor system architecture. With the rapid development of microelectronics and hardware,the use of ever faster micro processors and new architecture must be continued to meet tomorrow′s computing needs. New processor microarchitectures are needed to push performance further and to use higher transistor counts effectively.At the same time,aiming at different usages,the processor has been optimized in different aspects,such as high performace,low power consumption,small chip area and high security. SOC (System on chip)and SCMP (Single Chip Multi Processor) constitute the main processor system architecture.
出处 《High Technology Letters》 EI CAS 2003年第4期94-96,共3页 高技术通讯(英文版)
关键词 new microarchitecture development trend reusing explore parallelism 微处理机 系统结构 智能随机存储器 IRAM
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参考文献4

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二级参考文献42

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共引文献35

同被引文献41

  • 1江建慧,员春欣.芯片级系统的在线测试技术[J].计算机研究与发展,2004,41(9):1593-1603. 被引量:2
  • 2Fu Zhongchuan,Chen Hongsong,Cui Gang.MICROTHREAD BASED (MTB) COARSE GRAINED FAULT TOLERANCE SUPERSCALAR PROCESSOR ARCHITECTURE[J].Journal of Electronics(China),2006,23(3):461-466. 被引量:3
  • 3Premkishore Shivakumar,Michael Kistler,Stephen W Keckler,et al.Modeling the effect of technology trends on the soft error rate of combinational logic[C].2002 Int'l Conf on Dependable Systems and Networks,Bethesda,USA,2002 被引量:1
  • 4P P Shirvani,E J McCluskey.PADded cache:A new fault tolerance technique for cache memories[C].IEEE 17th VLSI Test Symposium,San Diego,1999 被引量:1
  • 5M Rebaudengo,M Sonza Reorda,M Violante.An accurate analysis of the effects of soft errors in the instruction and data caches of a pipelined microprocessor[C].Design Automation and Test in Europe Conference and Exhibition,Munich,Germany,2003 被引量:1
  • 6Shubhendu S Mukherjee,Joel Emer,Tryggve Fossum,et al.Cache scrubbing in microprocessors:Myth or necessity[C].The 10th Int'l Symp on Pacific Rim Dependable Computing (PRDC),Papeete,2004 被引量:1
  • 7B Nicolescu,P Peronnard,R Velazco,et al.Efficiency of transient bit-flips detection by software means:A complete study[C].The 18th IEEE Int'l Symp on Defect and Fault Tolerance in VLSI Systems (DFT'03),Cambridge,2003 被引量:1
  • 8A Avizienis.The N-version approach to fault-tolerant software[J].IEEE Trans on Software Engineering,1985,11(12):1491-1501 被引量:1
  • 9Z Alkhalifa,V S S Nair,N Krishnamurthy,et al.Design and evaluation of system level checks for on-line control flow error detection[J].IEEE Trans on Parallel and Distributed Systems,1999,10(6):627-641 被引量:1
  • 10B Nicolescu,R Velazco.Detecting soft errors by a purely software approach:method,tools and experimental results[C].Design Automation and Testing in Europe (DATE 2003).Messe Munich,Germany,2003 被引量:1

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