摘要
对Montgomery算法进行了改进,提供了一种适合智能卡应用、以RISC微处理器形式实现的RSA密码协处理器。该器件的核心部分采用了两个32位乘法器的并行流水结构,其功能部件是并发操作的,指令执行亦采用了流水线的形式。在10MHz的时钟频率下,加密1024位明文平均仅需3ms,解密平均需177ms。
A new VLSI architecture of RSA cryptography coprocessor based on the RISC microprocessor structure is designed by using a modified Montgomery algorithm The kernel of the device is two 32bit multipliers with pipelining structure, which operate concurrently At a clock rate of 10 MHz, it takes only 3 ms to encrypt and 177 ms to decrypt 1024bit message on average The designed performance and specifications of the RSA cryptography coprocessor makes it suitable for smart card applications
出处
《微电子学》
CAS
CSCD
北大核心
2003年第5期399-402,共4页
Microelectronics
