摘要
设计了一种针对Ｍｏｎｔｇｏｍｅｒｙ算法，以微处理器形式实现的ＲＳＡ协处理器。该协处理器中的功能部件是并发操作的，在一个周期内最多可同时发射三条指令，指令执行采用了二级和三级流水线混合的形式，协处理器和ＣＰＵ核之间通过交叉开关结构共享ＲＡＭ存储器。协处理器可以扩展为含多个乘法累加部件的结构。
Based on the microprocessor structure,an RSA coprocessor for improved Montgomery algorithm has been designed.The functional units of this coprocessor operate concurrently,and up to three instructions can be issued in one cycle.A mixed form of three stage and two stage pipelined structure is used for instruction execution,and the coprocessor and CPU core can share a common RAM memory through a set of switches under control.The structure of the coprocessor can be expanded to contain more than one multiplier accumulator units for higher performance.
出处
《微电子学》
CAS
CSCD
北大核心
1999年第1期62-68,共7页
Microelectronics
关键词
微处理器
智能卡
RSA算法
RSA协处理器
Microprocessor,Smart card,RSA algorithm,Montgomery algorithm,RSA coprocessor
