摘要
在分析了阈值电压的影响因素的基础上,分别通过工艺和电路两种途径调整阈值电压。在布尔乘法器设计中,对关键路径上的器件采用较低的阈值电压以提高速度,其余器件仍然保持较高的阈值电压以避免过大的漏电流,模拟结果表明1.0V工作时的功耗比3.3V降低近90%,而延时仍然保持在较合理的范围内,从而达到了保持性能和降低功耗的设计目标。
Power dissipation is regarded as one of the top concerns in VLSI dig ital system, and reducing working voltage is greatly helpful for reducing power consumption. Based on th e analysis of the factors affecting threshold voltage(VT), technology and circuit methods were used to a djust VT. Dual thresholdvoltages were applied in design of a low voltage Booth Multiplier, in which a small number of devices that are speed-critical operate at a relatively low VT to deal with time dela y,and other devices operateat higher VT to avoid excessive leakage current. Simulation result shows that power dissipation can be decreased to 10%when working voltage change from 3.3V to 1.0V, and time delay is still kept in restrict range.
出处
《功能材料与器件学报》
CAS
CSCD
2002年第4期407-410,共4页
Journal of Functional Materials and Devices
