摘要
针对目前高速通信中对高速率和低误码率的要求,本文设计并实现了一种具有纠错功能的8B/10B新型算法结构,输入数据先经过(7,4)BCH编码电路进行编码后再送入8B/10B编码器中进行编码,8B/10B编码电路采用数据码组和特殊码组并行编码结构实现。编码器通过Cadence的NCVerilog进行功能验证,完成电路仿真与实现。仿真结果表明,该电路可以正确实现8B/10B编码并具有纠正一位错码的能力。通过Synopsys的Design Compiler工具在SMIC 65nm工艺下进行综合,该编码器可达到在1GHz工作频率下占用逻辑资源面积为344μm2,具有运行速度快、占用逻辑资源小、误码率低的特点。
In consideration of the demand of high speed and low error rate in high-speed communication,a new 8B/10 Bencoder structure with the function of error correction was designed and implemented.The input data was encoded by a(7,4)BCH encoder firstly.Then,the output data generated by(7,4)BCH encoder was transferred to a 8B/10 Bencoder.The proposed 8B/10 B encoder architecture was realized based on pipeline and parallel processing.The proposed encoder completed function simulation and verification by Cadence NCVerilog.The simulation result shows that the circuit can realize the 8B/10 Bencoding correctly and has the ability to correct one-bit error.After being synthesized by 65 nm process of Synopsys Design Compiler,the proposed encoder can work at 1GHz frequency occupying a chip area of 344μm2.Hence,it can reduce the area of the circuit and improve the reliability of encode.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2016年第4期332-337,共6页
Research & Progress of SSE
基金
333高层次人才培养工程专项资助(2007124)
广东省部产学研合作引导项目资助(2009B090300416)
