摘要
针对硬件实现高位RSA加密算法成本比较高的问题,在传统的基4蒙哥马利(Montgomery)算法上进行改进。首先引入CSA加法器快速完成大数的加法计算;然后在后处理上做优化,以减少每次蒙哥马利计算的大数个数;最后在计算RSA加密算法时加入了流水线,在并行执行RSA加密的条件下降低硬件资源的使用。在Xilinx XC7K410T系列的FPGA开发板上的实验结果表明,在保证加密速率的前提下,改进的RSA加密算法结构使用的硬件资源是原来并行结构的1/2,而且可以在更高的频率下工作。
To address the high cost of implementing long-bits RSA encryption algorithms in hardware,improvements have been made to the traditional radix-4 Montgomery algorithm.Firstly,a Carry-Save Adder(CSA)is introduced to efficiently complete large numbers of addition computations.Optimization is then carried out in post-processing to reduce the number of large numbers to be calculated at each Montgomery computation.Finally,a pipelining technique is incorporated into the RSA encryption algorithm for parallel execution,thereby reducing the use of hardware resources.Experimental results on a Xilinx XC7K410T FPGA development board demonstrate that while maintaining encryption speed,the hardware resources used by the improved RSA encryption algorithm are only half of those of the previous parallel structure and can operate at higher frequencies.
作者
杨龙飞
卢仕
彭旷
Yang Longfei;Lu Shi;Peng Kuang(School of Microelectronics,Hubei University,Wuhan 430062,China)
出处
《电子技术应用》
2024年第1期66-70,共5页
Application of Electronic Technique
基金
湖北省教育厅科学技术研究计划青年人才项目(Q20201006)
湖北省自然科学基金面上青年项目(2020CFB266)。
