摘要
基于CIOS模乘算法和Montgomery powering ladder模幂算法,设计了模幂电路,能进行密钥长度可配置的模乘、模幂、模加和模减运算.在50 MHz和SIMC13LL工艺库条件下对模幂电路进行DC综合,面积为16.1千门,吞吐率为10kb/s,30 MHz下Primetime PX分析功耗2.87mW,满足智能卡对速度、功耗、面积等指标需求.与近几年文献中的RSA模乘器相比,所设计的模乘电路具有最小的"功耗×面积/吞吐率",资源利用率高.
In this paper,we design a key-length-configurable modular exponentiation based on CIOS modular multiplication algorithm and Montgomery powering ladder exponentiation algorithm.The long integer modular exponentiation circuit is synthesized by Synopsys Design Compiler under the clock frequency of 50 MHz and SMIC13 LL technology at a cost of 16.1kgates and throughput is 10kb/s and Primetime PX power report shows that the average power consumption of 30 MHz is 2.87 mW,which achieves the requirements of speed,power consumption and circuit area of smart card.The modular multiplication circuit proposed by this thesis achieves high resource utilization rate and smallest 'power×area/throughput' in comparison with modular multiplication of systolic array architectures.
出处
《微电子学与计算机》
CSCD
北大核心
2015年第2期37-41,共5页
Microelectronics & Computer
关键词
智能卡
蒙哥马利模乘
模幂
非对称算法
smart card
Montgomery modular multiplication
modular exponentiation
asymmetric encryption
