摘要
随着高性能计算芯片的集成度不断提高以及工艺的进步,金属连线的宽度越来越窄,芯片电源网络上电阻增加和高密度的逻辑门单元同时有逻辑翻转动作时会在电源网络上产生电压降(IR Drop),导致芯片产生时序问题,甚至可能发生逻辑门的功能故障。基于Cadence实现工具Innovus的flash PG flow完成对于PG网络的综合实现与快速迭代,并利用auto reinforce PG和trim PG从两方面实现了对高性能CPU核的电压降与时序之间的trade-off,完成从floorplan到PR(Placement and Route)阶段针对PG网络的全流程优化。结果表明,在相同机器资源的前提下,flash PG flow最高可将powerplan的速度提升至原来的10倍,在top level的design上提升尤为明显,能有效节约设计初期对PG mesh的探索时间。而auto reinforce PG和trim PG则分别通过补强IR薄弱区域的PG和修剪冗余PG两方面针对性地修复设计66%的dynamic IR Drop违例,同时为设计提供更多绕线资源,达到不恶化时序和DRC (Design Rule Check)的目的。
With the continuous improvement of the integration of high-performance computing chips and the advancement of technology,the width of metal wires is getting narrower and narrower,and the voltage drop(IR drop)will occur on the power network when the resistance on the chip power network increases and the high-density logic gate unit has a logic flip action at the same time,resulting in timing problems in the chip,and even the functional failure of the logic gate may occur.Based on the flash PG flow of the Cadence implementation tool Innovus,this paper completes the comprehensive implementation and rapid iteration of the PG network,and uses auto reinforce PG and trim PG to realize the trade-off between the voltage drop and timing of the high-performance CPU core from two aspects,and completes the whole process optimization of the PG network from floorplan to PR(Placement and Route)stage.The results show that under the premise of the same machine resources,flash PG flow can increase the speed of powerplan up to 10 times the original,especially in the design of the top level,which can effectively save the exploration time of PG mesh in the early stage of design.Auto reinforce PG and trim PG repair 66%of the dynamic IR drop violations by reinforcing the PG of the weak IR area and trimming the redundant PG respectively,and at the same time provide more winding resources for the design to achieve the purpose of not deteriorating the timing and DRC(Design Rule Check).
作者
姜姝
杨超
吴驰
Jiang Shu;Yang Chao;Wu Chi(Jaguar Microsystems,Shanghai 201210,China)
出处
《电子技术应用》
2023年第8期36-41,共6页
Application of Electronic Technique
