摘要
数字锁相环技术在数据通信、无线电电子学等众多领域得到了广泛应用,同时也是FPGA片上系统非常重要的关键部件。在分析模拟锁相环性能的基础上,介绍了数字锁相环的工作原理,并利用Quartus设计环境,采用VHDL语言实现了锁相环的全数字电路设计,通过软件自带的仿真工具,对重点模块及完整顶层电路进行了仿真分析,仿真结果验证了设计的正确性。
Digital phase-locked loop technology has been widely used in many fields such as data communication and radio electronics,and it is also a very important key component of FPGA system on chip.Based on the analysis of simulation performance of phase-locked loop,this paper introduces the working principle of digital phase locked loop,and uses the Quartus design environment,adopts VHDL language to realize the full digital phase-locked loop circuit design.Through the built-in simulation tools of the software,the key module and the complete top-layer circuit are simulated and analyzed,the simulation results verify the validity of the design。
作者
杨翠娥
Yang Cuie(Taiyuan Institute of Technology,Taiyuan Shanxi 030008,China)
出处
《山西电子技术》
2023年第2期74-76,共3页
Shanxi Electronic Technology
关键词
锁相环
FPGA
仿真
phase-locked loop
FPGA
simulation
