摘要
竞争冒险作为数字电路设计中经常会遇到的现象,存在可能导致高速电路或毛刺敏感电路的逻辑错误。以k变模可逆计数器设计中出现的竞争冒险现象为例,从程序、仿真波形、综合电路等方面较为详细地介绍了应用VHDL进行数字电路设计中竞争冒险现象产生的原因,并提出了采用同步时序电路设计的原则消除竞争冒险的方法。
Race and hazard often occur in digital circuit design, which always effect circuit logic function for high speed circuit or race sensitive circuit. This article takes changeable Modulo- k Reversible Counter as an example, analyzes the reason of race and hazard occured in digital circuit design with VHDL language from many guises, such as the design of program, simulation wave and synthesis circuit, and gives the asynchronous sequential logic design method for clearance race and hazard.
出处
《现代电子技术》
2007年第24期185-186,190,共3页
Modern Electronics Technique
关键词
竞争冒险
计数器
VHDI
同步时序电路
race and hazard
counter
VHDL
asynchronous sequential circuit
