摘要
基于设计一种应用于SOC芯片的线性稳压器的目的,采用在误差放大器和功率管之间插入快速响应缓冲级的方法,结合单级折叠共源共栅放大电路和PMOS管功率器件,组成一种优化电路结构。通过SMIC的0.13μm工艺库进行设计仿真,结果表明,在典型条件下,输出电压为1.204 V。输入电压2.5~3.6 V时,供电电压调整率为1 mV/V。负载电流在10μA~20 mA变化,上升下降时间为1 ns时,响应时间小于1.15μs,负载调整率为19.8μV/mA,最大负载电流为20 mA。负载电容为2~100 pF,静态工作电流为6.97μA。PVT条件下,输出电压为1.2 V±1.04%。该电路各性能参数均满足设计指标要求,且结构简单,易于实现,无需片外电容,瞬时响应快,静态电流小,可为数字电路提供稳定的低压电源,具有较高应用价值。
Based on the purpose of designing a linear voltage regulator applied to SOC chips,using the method of inserting a fast⁃response buffer stage between the error amplifier and the power tube,combined with a single⁃stage folded cascode amplifier circuit and a PMOS tube power device,form an optimized circuit structure.Design and simulation using SMIC’s 0.13μm process library.The results show that under typical conditions,the output voltage is 1.204 V.The power supply voltage regulation rate is 1 mV/V when the input voltage is 2.5~3.6 V.The response time is less than 1.15μs when the load current varies from 10μA to 20 mA and the rise and fall time is 1ns,at that time the load regulation rate is 19.8μV/mA,the maximum load current is 20 mA.The load capacitance is 2~100 pF,and the quiescent current is 6.97μA.Under the PVT conditions,the output voltage is 1.2 V±1.04%.The performance parameters of the circuit meet the design indicators,and the structure is simple,easy to implement,without off⁃chip capacitors,fast transient response,small quiescent current,it can provide stable low⁃voltage power supply for digital circuits,and has high application value.
作者
律博
LV Bo(Dalian Neusoft University of Information,Dalian 116023,China)
出处
《电子设计工程》
2023年第8期166-170,共5页
Electronic Design Engineering
关键词
SOC
线性稳压器
快速响应缓冲级
PVT
片外电容
数字电路
SOC
linear voltage regulator
fast⁃response buffer stage
PVT
external capacitance
digital circuit
