摘要
文章基于130 nm SiGe BiCMOS工艺设计实现了一种1×7的二分频器链,链路前四级采用电流型逻辑(current mode logic,CML)实现,后三级采用电压型逻辑(voltage mode logic,VML)实现;并设计了电平转换模块,解决2种形式电路匹配问题,实现链路前后的级联。此外完成了分频器链的版图设计,尺寸为1146×647μm^(2),并对分频器进行仿真实验,在20 GHz的输入信号下,得到156.25 MHz的信号输出,实现128分频。最后进行系统仿真,将该分频器链应用到锁相环(phase locked loop,PLL)系统的反馈回路中,当输入参考信号为156.25 MHz时,经过400 ns后PLL进入锁定状态,输出信号频率为20 GHz,实现了128倍的频率放大。
Based on 130 nm SiGe BiCMOS process,a 1×7 divider chain is designed and implemented.The first four stages of the link are implemented by current mode logic(CML),and the last three stages are implemented by voltage mode logic(VML).The level conversion module is designed to solve the matching problem of the two types of circuits and realize the cascade before and after the link.In addition,the layout design of the divider chain is completed,the size is 1146×647μm^(2),and the frequency divider is simulated.Under the input signal of 20 GHz,156.25 MHz signal output is obtained and 128 frequency division is realized.Finally,the divider chain is applied to phase locked loop(PLL)feedback circuit.When the input reference signal is 156.25 MHz,the PLL is locked after 400 ns,and the signal frequency of output is 20 GHz,which achieves 128 times frequency amplification.
作者
董飞翔
何晴
李庄
陶小辉
曹锐
桑磊
DONG Feixiang;HE Qing;LI Zhuang;TAO Xiaohui;CAO Rui;SANG Lei(School of Electronic Science and Applied Physics, Hefei University of Technology, Hefei 230601, China;No.38 Research Institute, China Electronics Technology Group Corporation, Hefei 230088, China)
出处
《合肥工业大学学报（自然科学版）》
CAS
北大核心
2022年第2期203-207,共5页
Journal of Hefei University of Technology：Natural Science
基金
国家自然科学基金资助项目(40000009)
安徽省自然科学基金资助项目(10000007)
教育部新世纪优秀人才支持计划资助项目(NCET-00-0001)。
