摘要
随着嵌入式系统小型化和模拟数字/数字模拟转换器(ADC/DAC)性能需求的日益增长,如何在减小系统体积和功耗的前提下,提高ADC/DAC信号传输的可靠性,增加功能可配置性和信号处理可重构性,成为一大难题。为此,设计了一款基于FPGA的系统级封装(SiP)原型验证平台,该SiP基于ADC+SoC+DAC架构,片上系统(SoC)内部以PowerPC470为处理器,集成了多种通用外设接口和可重构算法单元。在搭建的FPGA平台上进行裸机IP和基于可重构IP的ADC/DAC设计功能的验证。通过软硬件协同验证实验,证明了该类SiP架构能够有效降低走线延时和噪声干扰,提高信号传输的可靠性,丰富的外设接口提高了ADC/DAC的可配置性,集成的可重构算法模块增加了ADC/DAC信号处理可重构性,为后续集成更多器件该类型SiP的设计和验证奠定了一定的技术基础。
With the growing demand of embedded system miniaturization and the performance of analog-to-digital/digital-to-analog converter(ADC/DAC),it is a big problem how to improve the reliability of ADC/DAC signal transmission,increase the function configurability and signal processing reconfigurability on the premise of reducing system volume and power consumption.Thus,this paper designs a system in package(SiP)prototype verification platform based on FPGA,used to verify the feasibility and reliability of this SiP architecture.This SiP is based on the ADC+SoC+DAC architecture,PowerPC470 is the internal processor of system on chip(SoC),which integrates various common peripherals and the reconfigurable algorithm unit.The design and function verification of bare machines IP and ADC/DAC based on reconfigurable IP are carried out on the built FPGA platform.It is verified that this SiP can effectively reduce routing deley and noise interference to improve the transmission reliability of signal,rich peripheral interface improves configurability of ADC/DAC,integrated reconfigurable algorithm increases the reconfigurable performance of signal processing through software and hardware co-verification experiment,laying a basic technical foundation for later SiP design and testing for integrating more devices.
作者
杨楚玮
张梅娟
侯庆庆
Yang Chuwei;Zhang Meijuan;Hou Qingqing(The 58th Research Institute,CETC,Wuxi 214035,China)
出处
《电子技术应用》
2022年第1期84-88,93,共6页
Application of Electronic Technique
