摘要
目前大多数JT1DS信号检测设备采用了基于软件无线电理念的中频采样架构,该架构的接收机存在体积大、成本高及设备性能受前端模拟器件影响大等问题。文章阐述了利用一种基于射频直采架构的宽带接收机实现JTIDS信号检测的设计方案,该接收机采用单通道ADC对JTIDS信号全频段进行射频采样,并在FPGA内实现信号的检测,具有大带宽、大动态等特点,在保证性能的同时解决了现有设备体积大、成本高等问题。
At present,most of the JTIDS checking equipment is based on the IF sampling architecture of software radio.The receiver of this architecture has many problems,such as large volume,high cost and great influence of analog front-endon the performance of the equipment.This paper expounds a JTIDS auto-checking design based on wide-band receiver of RF sampling,the receiver samples JTIDS signal by single channel ADC,and within the FPGA to realize signal identification,has the characteristic such as wide band,large dynamic,solves the existing equipment at the same time the performance of large volume and high cost problems.
作者
王峰
WANG Feng(No.36 Research Institute of CETC,Jiaxing Zhejiang 314033,China)
出处
《通信对抗》
2020年第4期19-22,共4页
Communication Countermeasures
基金
国防基础科研计划资助项目(JCKY2017210A001)。
