期刊文献+

非气密倒装焊陶瓷封装热特性分析及测试验证

Thermal Characteristic Analysis and Test Verification of Nonhermetic Flip-chip Ceramic Package
下载PDF
导出
摘要 首先,针对非气密倒装陶瓷球栅阵列封装,设计了典型的结壳热阻测试的器件;其次,基于器件模型,采用有限元建立三维热模型仿真结壳热阻θj-top和θj-bottom值;然后,分析芯片尺寸、导热胶和热沉盖板材料对结壳热阻的影响;最后,针对一款典型的测试器件进行了结壳热阻测试,验证了仿真结果的准确性。 Firstly,a typical junction-to-case thermal resistance test device is designed for nonhermetic flip-chip ceramic ball grid array package.Next,based on the device model,a three-dimensional thermal model is established by using finite element to simulate the junction-to-case thermal resistance,that is,the values of Qj-topand Qj-bottom.Then,the influence of chip size,conductive adhesive and heat sink cover material on junction-to-case thermal resistance is analyzed.Finally,a junction-to-case thermal resistance test is performed for a typical test device,which verifies the accuracy of the simulation results.
作者 王波 杨明 高娜燕 王剑峰 WANG Bo;YANG Ming;GAO Nayan;WANG Jianfeng(No.58 Research Institute of CETC,Wuxi 214035,China)
出处 《电子产品可靠性与环境试验》 2020年第S01期90-93,共4页 Electronic Product Reliability and Environmental Testing
关键词 非气密 倒装 陶瓷 结壳热阻 热特性 仿真 non-hermetic flip-chip ceramic junction-to-case thermal resistance thermal characteristics simulation
  • 相关文献

参考文献4

二级参考文献16

  • 1黄卫东,罗乐.封装结构与材料导热系数对FC-BGA热性能的影响[J].电子与封装,2007,7(8):11-16. 被引量:3
  • 2RAVI K, MUJUMDAR A S. Thermal analysis of a chip ceramic ball grid (CBGA) package [J]. Microeleetron Reliab, 2008, 48: 261-271. 被引量:1
  • 3CHEN K H, HOUNG K H, CHIANG K N. Thermal resistance analysis and validation of flip chip PBGA package [J]. Mieroelectron Reliab, 2006, 46: 440-448. 被引量:1
  • 4KANDASAMY R, MUJUMDAR A S. Interface thermal characteristics of flip chip packages-A numerical study [J]. Appl Therm Eng, 2009, 29: 822-829. 被引量:1
  • 5EIA. JESD51-8 Integrated circuit thermal test method environmental conditions-junction to-board [S]. USA: EIA, 1999. 被引量:1
  • 6EIA. JESD51-12 Guidelines for reporting and using electronic package thermal information [S]. USA: EIA, 2005. 被引量:1
  • 7GJB548B一2005,微电子器件试验方法和程序[S]. 被引量:2
  • 8GB/T14862-93.半导体集成电路封装结一外壳热阻测试方法[S]. 被引量:1
  • 9EIA/JESD51-14. Transient Dual Interface Test Method for the Measurement of the Thermal Resistance Junction to Case of Semiconductor Devices with Heat Flow Trough a Single Path [S]. ELECTRONIC INDUSTRIES ASSOCIA- TION, 1995. 被引量:1
  • 10Andrds Poppe, Yan Zhang, GcxborFarkas. Themaal characterization of multi-die packages [C]. 2006 Electronics Packaging Technology Conference, 2006:1-6. 被引量:1

共引文献15

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部