摘要
随着深度学习的快速发展,神经网络算法被广泛应用于图像处理领域。由于硬件算力限制了神经网络的实现与应用,基于FPGA的神经网络硬件加速器相继被提出。U-Net网络作为一种特殊的卷积神经网络,在生物医学图像分割方向具有重要的意义。U-Net网络的运算瓶颈是卷积运算,采用循环展开、循环流水等硬件电路设计方法,通过提高FPGA内部硬件资源利用率增加卷积运算硬件加速器的并行度,提升硬件系统的整体运算性能。最终在Pynq-Z1异构平台上实现了卷积运算硬件加速器的设计,完成了整个U-Net网络的软硬件系统开发。试验表明,整个U-Net网络硬件加速器的运算性能提升为原来的19.690倍,是一种有效的神经网络加速方案。
With the rapid development of deep learning,neural network algorithm is widely used in the field of image processing.Since the hardware computation ability has limited the implementation and application of neural networks,FPGA-based neural network hardware accelerators have been proposed one after another.As a special convolutionalneural network,U-Net network is of great significance in biomedical image segmentation.The computation bottleneck of U-Net network is the convolution computation unit.The hardware circuit design methods such as loop unrolling and loop pipelining are used to improve the parallelism of convolution computation hardware accelerator and the overall computation performance of hardware system by consuming FPGA internal hardware resources.Finally,convolution computation hardware accelerator design of the U-Net network is realized on the Pynq-Z1 heterogeneous platform,and the software and hardware system development of the entire U-Net network is completed.The experiment result shows that the performance of the U-Net hardware accelerator is 19.690 times of the original,which is an effective neural network acceleration scheme.
作者
梅亚军
王唯佳
彭析竹
MEI Yajun;WANG Weijia;PENG Xizhu(School of Electronic Science and Engineering,University of Electronic Science and Technology of China,Chengdu 610054,China)
出处
《电子与封装》
2020年第6期38-43,共6页
Electronics & Packaging
基金
四川省科技计划项目(2018GZDZX0001)。
