摘要
介绍了一种基于锁相环的多相位时钟实现小数分频方法,利用一个可配置计数步长的相位选择计数器进行循环计数,计数器的值用来控制相位选择器的选择信号。相位选择器的输入为锁相环输出时钟的多个相位版本,相位选择器的输出既作为相位选择计数器的计数时钟,又作为整数分频器的输入时钟。计数器不断地在循环累加,相位选择器的输出时钟相位随之发生变化。整数分频器的输入时钟被不断地插入了一个相位差,其输出实现了分辨率为0.125的小数分频。最后对电路进行了仿真验证。
A method based on phase-locked loop(PLL) multi-phase clock is proposed. It is introduced to realize fractional frequency division. A configurable counting step phase selection counter is used for cyclic counting. The value of the counter controlles selection signal of the phase selector. The phase selector’s input is multiple phase versions of the PLL output clock. The output is both the counting clock of phase selection counter and the input clock of the integer frequency divider. The phase selector’s output clock phase changes as the counter accumulates in cycles. So the input clock of the integer frequency divider is constantly inserted a phase difference, and its output realizes the resolution of 0.125 fractional frequency divider. The results are verified by simulation.
作者
涂波
王兴宏
TU Bo;WANG Xinghong(East Technologies,Inc.9 Wuxi 214072,China)
出处
《电子与封装》
2020年第1期33-36,共4页
Electronics & Packaging
关键词
锁相环
小数分频
计数器
phase-locked loop
fractional frequency divider
counter
