摘要
为了缓解多通道SerDes中高频时钟信号在长距离传输中引入的噪声过大和功耗过高的问题,设计了一种应用于多通道的低功耗低抖动两级锁相环结构;同时为了进一步降低噪声性能,在第2级锁相环中设计了一种采样鉴相器。该设计将第1级LC振荡器锁相环产生的低频时钟信号(3.125 GHz)传输到各通道收发机后,将该信号作为第2级参考信号,再采用小面积的环形振荡器锁相环产生正交的高频时钟(12.5 GHz),这种结构降低了高频时钟在片上长距离传输的距离,提高了收发机的时钟质量;此外该技术避免了使用高频缓冲器,降低了功耗。其中第2级锁相环通过无分频鉴相技术提高了第2级环振锁相环的噪声性能。该时钟发生器电路整体功耗为100 mW,第1级锁相环相位噪声拟合后为-115 dBc/Hz,第2级环形振荡器电路在1 MHz处相位噪声为-79 dBc/Hz,锁相环电路产生的时钟信号整体抖动为2.7 ps。正交时钟偏差在300 fs以内。相比传统时钟发生器,该设计性能有较大提高,功耗有明显降低,适合应用于100 Gbps SerDes中。
In order to alleviate the problem of excessive noise and excessive power consumption introduced by long-distance transmission of high-frequency clock signals in multi-channel SerDes,a low-power low-jitter two-stage phase-locked loop applied to multi-channel serial interface is designed,Simultaneously,this design is used to transmit the low-frequency clock signal(3.125 GHz)generated by the first-stage LC oscillator phase-locked loop to each channel transceiver,this signal is taken as the second-level reference signal,and then a small-area ring oscillator phase-locked loop is used to produce an orthogonal high-frequency clock(12.5 GHz).This structure reduces the distance that the high-frequency clock transmits over long distances on the chip,and improves the clock quality of the transceiver.In addition,this technology avoids the use of high-frequency buffers and reduces power consumption.In order to further reduce the noise performance,a sampling phase detector is designed in the second-stage phase-locked loop.This technology improves the noise performance of the second-stage ring-vibration phase-locked loop by means of no-frequency phase discrimination.The overall power consumption of the clock generator circuit is 100 mW,the phase noise of the first-stage phase-locked loop is-125 dBc/Hz,and the phase noise of the second-stage ring oscillator circuit is-79 dBc/Hz at 1MHz.The overall jitter of the clock signal generated by the circuit is 2.7 ps.The quadrature clock skew is within 300 fs.
作者
辛可为
吕方旭
王建业
王和明
XIN Kewei;LYU Fangxu;WANG Jianye;WANG Heming(Air and Missile Defense College,Air Force Engineering University,Xi’an 710038,China)
出处
《空军工程大学学报（自然科学版）》
CSCD
北大核心
2019年第5期64-69,共6页
Journal of Air Force Engineering University(Natural Science Edition)
关键词
两级锁相环
采样鉴相器
环形振荡器
多通道高速串行接口
two-stage phase-locked loop
sampling phase detector
ring oscillator
multi-channel high-speed serial interface
