摘要
针对时钟数据恢复电路(CDR)中相位插值器的非线性使得时钟抖动增大的问题,提出了一种基于非等值电流源阵列的线性相位插值器。根据插值器输出时钟相位与尾电流权重的反函数关系,在传统相位插值器的基础上调整尾电流阵列中每个电流源的设计比例,并将控制管用作共栅管来提高电流源的匹配度和稳定性,从而实现了输出时钟相位与控制信号的线性关系,提高了CDR的调节精度并降低了恢复时钟的抖动。采用0.25μm CMOS工艺设计了一款基于线性相位插值器的CDR。仿真结果表明:传统结构插值器的最大相位误差为63.68%,而所提出的线性相位插值器的最大相位误差仅为9.44%,可有效地降低CDR输出时钟的抖动。
A linear phase interpolator based on non-equal current source array is presented to solve the problem of increasing clock jitter caused by the non-linearity of phase interpolator in clock and data recovery circuit.According to the inverse function relationship between the phase of the output clock and the weights of the tail current sources,the ratio of each current source in the tail current source array of the interpolator is adjusted elaborately based on the traditional phase interpolator.Moreover,the control transistor is used as a common gate transistor so as to improve the matching degree and the stability of the current source.Thus the linear relation between the phase of the output clock and the control signals is realized.The regulation precision of CDR is improved while the jitter in recovering clock is reduced.A clock and data recovery circuit based on the presented linear phase interpolator is designed using the 0.25μm CMOS technology.Simulation results show that the maximum phase error of the proposed linear phase interpolator is 9.44%,while the maximum phase error of the traditional interpolator is 63.68%,that is,the presented interpolator significantly reduces the clock jitter of the CDR.
出处
《西安交通大学学报》
EI
CAS
CSCD
北大核心
2016年第2期48-54,共7页
Journal of Xi'an Jiaotong University
基金
国家自然科学(61474092)
陕西省科技计划资助项目(2014K05-14)
模拟集成电路重点实验室基金资助项目(140C09044)
关键词
时钟恢复
相位插值
线性度
抖动
clock recovery
phase interpolation
linearity
jitter
