摘要
提出了一种具有良好抑制输入数据抖动性能的突发模式相位插值型时钟数据恢复电路。在传统相位插值型电路结构的基础上,在采样保持电路与相位插值电路之间加入一级求和电路,理论分析和仿真结果表明,恢复时钟相位变化受输入数据抖动的影响明显减小。电路基于1.1 V SMIC 40nm 1P8M CMOS工艺搭建,其数据率为6.25Gb/s,消耗功耗为6.7 mW,版图面积为0.35mm^2。
A phase-interpolator（PI）-based burst-mode clock and data recovery（BMCDR）using adjacent sampling summing method was presented,which had a strong ability of suppressing the jitter of input data.Based on the typical PI-based BMCDR,a summing circuit was inserted between the sample-and-hold（S/H）circuit and the PI circuit.The theory analysis and the simulation results showed that the jitter transfer from input data to output recovered clock was suppressed.The BMCDR was implemented using the 1.1 V SMIC 40 nm 1P8 M CMOS process.The circuit operated at 6.25Gb/s.The power dissipation was 6.7mW.The layout area was 0.35mm^2.
出处
《微电子学》
CAS
CSCD
北大核心
2016年第2期247-250,共4页
Microelectronics
基金
中科院A类战略性先导科技专项资助项目(面向感知中国的新一代信息技术研究)(XDA06010402)
