摘要
FPGA高速电路设计中,面对由信号传输延时的不确定性引发的数据错位或混乱问题,本文介绍了一种逻辑单元延时值的测量方法,从而给出了一种解决该问题的方案。首先分析了如何用FPGA器件中的逻辑单元构建延时器、同步器来改善信号传输延时时差;然后给出了测量逻辑单元延时值的实用电路,并用该方案实现了数控延时器、触发振荡器、测时游标的设计。
In the design of FPGA high-speed circuit, data dislocation or confusion can be caused by the uncertainty of signal transmission delay. This paper introduces a method for measuring the value of logic cell delay, thus providing a solution to the above problem. First, analysis is made concerning how to build delay device and synchronizer by using logic units in FPGA so as to improve signal transmission delay.Then a practical circuit for measuring the delay value of logic unit is presented and applied to the design of NC delayer, flip flop oscillator and timingvernier.
作者
周玉鸿
蔡昌勇
董晓红
ZHOU Yuhong;CAI changyong;DONG Xiaohong(College of Electronical and Information Engineering,Chengdu Aeronautic Polytechnic,Chengdu 610100;Sichuan College-enterprise Cofounded Innovation Base of“Avionics”Applied Technology,Chengdu 610100)
出处
《成都航空职业技术学院学报》
2019年第3期46-48,58,共4页
Journal of Chengdu Aeronautic Polytechnic
关键词
逻辑单元
传输延时
延时测量
logic cell
transmission delay
delay measurement
