摘要
针对集成电路SOC芯片对PIN脚资源的限制以及用于敏感信息防护的安全芯片的应用领域,需要使用片上LDO和片上滤波电容的方案来为内核供电。由于LDO的低带宽导致带来相应速度问题,需要用片上滤波电容来提供数字电路瞬态翻转的能量,要使用纳法级的滤波电容占用极大的芯片面积,使得布局和LDO都在项目后期完成设计,导致芯片布局的迭代次数增加。深刻理解数字电路的工作原理和设计流程,提出了一种全新的设计流程和电容估算方法,在项目前期就完成片上电容的精确预估,从而可以早期进行LDO和芯片布局设计,减少了迭代周期,节省了芯片研发时间,并且通过仿真和测试,验证了提出了估算方法具有较好的预估精度。
Aiming at the limitation of SOC′s pin number,and in security IC applications,on chip capless LDO and on chip decouple capacitor were preferred for suppling digital cores power.But On Chip Capless LDO′s finite bandwidth limited it responses sharp current pulses existed in digital core,huge on chip decouple capacitors of several nano farads are necessary for these situations.These on chip capacitors occupy significant chip area,so these capacitors must be mapped out in the whole chip floorplan and so did LDO designs.In conventional design flow,the on chip capacitor′s size was confirmed after P&R with power simulations at the late design procedure,which results in iterations of LDO design and whole chip floorplan distribution.A new accurate method was given based on deeply understanding digital circuit how to work in order to estimate the values of on chip capacitors at the early procedure of the flow,so the floorplan of the chip and LDO design could be started earlier,the iteration of these procedure was limited to one time.This method was succeeded applied in one SOC design,the post simulation and test results show that the estimated on chip capacitors are very accurate.
作者
何洋
马永旺
侯佳力
王小曼
胡毅
冯曦
唐晓柯
He Yang;Ma Yongwang;Hou Jiali;Wang Xiaoman;Hu Yi;Feng Xi;Tang Xiaoke(State Grid Key Laboratory of Power Industrial Chip Design and Analysis Technology,Beijing SmartChip Microelectronics Technology Co.,Ltd.,Beijing 100192,China;Beijing Engineering Research Center of High-reliability IC with Power Industrial Grade,Beijing Smart-Chip Microelectronics Technology Co.,Ltd.,Beijing 100192,China)
出处
《电子技术应用》
2019年第2期23-26,共4页
Application of Electronic Technique
