摘要
在系统Raptor码译码中,针对高复杂度的高斯消元运算导致译码延时大、吞吐率低的问题,提出一种低延时高吞吐率的降维并行译码方案。该方案采用仅对少量丢包译码的低复杂度降维运算,替换对全部源数据包译码的高斯消元运算,降低译码延时;并针对降维译码采用全并行的硬件结构实现,提高译码吞吐率。依此方案,在Xilinx FPGA XC7K410T平台上实现系统Raptor译码器。测试结果表明,当网络丢包率在10-2以下时,译码数据吞吐率达到3.5Gbps,是相同硬件下采用高斯消元译码实现的80倍以上。
The high complexity Gaussian elimination(GE)algorithm of the systematic raptor decoding results in its high latency and low throughputs.A high efficiency parallel dimensionality-reduction decoding scheme is presented in this paper.The proposed scheme uses low complexity dimensionality-reduction algorithm to decode lost packets to replace the GE algorithm which decodes all source packets.Meanwhile,a full parallel structure for the decoding is proposed to implement the dimensionality-reduction-algorithm.At last,the decoder is implemented on Xilinx FPGA XC7K410T.The test results show that the scheme can achieve a 3.5 Gbps throughput within a 10-2 packet loss probability,which is 80 times better than that of the GE algorithm.
作者
任雁鹏
管武
梁利平
REN Yan-peng;GUAN Wu;LIANG Li-ping(Institute of Microelectronics,Chinese Academy of Sciences Chaoyang Beijing 100029;School of Microelectronics,University of Chinese Academy of Sciences Huairou Beijing 100049)
出处
《电子科技大学学报》
EI
CAS
CSCD
北大核心
2018年第6期814-818,共5页
Journal of University of Electronic Science and Technology of China
基金
国家自然科学基金面上项目(61471354)
关键词
数字喷泉码
降维译码
并行译码
系统Raptor码
digital fountain code
dimensionality-reduction decoding
parallel decoding
systematic raptor codes
