摘要
介绍了SDRAM的结构、时序和有关概念。在该基础上,基于自顶向下设计思想,把控制器模块划分为两个部分:内部命令产生、命令输出。基于verilog实现这两部分模块电路,并完成顶层实体。测试表明,该控制器是有效的。
The structure, timing and related concepts of SDRAM are introduced in this paper. After that, Based on the topdown design idea, the controller module is divided into two parts:the internal command generation、command output. The two module circuits as well as top layer entity are realized Based on verilog, The test shows that the controller is worked.
出处
《电脑知识与技术（过刊）》
2017年第11X期236-238,共3页
Computer Knowledge and Technology
