摘要
位同步是通信系统的核心,同步系统的性能关系到通信质量的好坏。为适应实际工程要求,实现可变速率的码元同步,笔者对超前-滞后型数字锁相环进行改进,具体做法是通过对寄存器配合扣除门和添加门的控制,借助MATLAB软件对该方法进行仿真,并在ISE14.7环境下编写VHDL和Testbench代码,用Modelsim观察代码仿真结果。结果表明:同步码元速率最小为1Kbps最大为20Mbps,并以最小步长0.5Kbps变化的可变速率可实现快速同步。实际工程结果在最后已给出,同时经过仿真和实际工程结果双重验证,判定该方法正确可行,并成功应用到某项目中。
Synchronization is the core of the communication system and the performance of synchronous system is related to the communication quality. In order to meet the requirements of practical engineering and to achieve variable rate symbol synchronization,the author makes an improvement on the lead-lag digital phase-locked loop. Specifically,the author controls register,making it work in with deducting gate and adding gate,makes a simulation of this method by MATLAB,then writes VHDL and Testbench code under ISE14. 7 environment,furthermore observe the code simulation results. The result shows： that means can achieve fast synchronization,when the minimum is synchronous symbol rate 1 Kbps,the maximum is 20 Mbps and the smallest step change of variable rate is 0. 5 Kbps. Actual project results are given in the final paper. This method was double verified by simulation and actual project results,which was right and feasible,meanwhile,was applied to a project successfully.
作者
孙海波
徐元哲
杨柳青
SUN Hai-bo;XU Yuan-zhe;YANG Liu-qing(Sehool of Automation Engineering,Northeast Power University,Jilin 132012,China;School of Electronics and Communication Engineering,Hainan Tropical Ocean University,Haikou 132012,China;Shanghai Engineering Center for Mierosatellite,Shanghai 200000,China)
出处
《电气开关》
2018年第3期36-42,共7页
Electric Switchgear
关键词
位同步
可变速率
数字锁相环
FPGA
bit synchronization
variable rate
digital phase-locked loop
FPGA
