摘要
多核处理器主要包括两种,即对称多核处理器(SMP)和非对称多核处理器(AMP)。目前大部分通用多核处理器是SMP,各个CPU是平等的,共享操作系统、内存和外设等资源;AMP大多是嵌入式多核处理器采用的架构,由一个主CPU控制系统运行和资源分配,从CPU执行主CPU的命令或者预定义任务。Zynq是Xilinx推出的全可编程芯片,是以ARM为核心,以FPGA作为可编程外设的全新架构处理器。Zynq包括两个可以同时独立运行可执行程序的Cortex-A9处理器,是一种非对称多核芯片。主处理器控制整个系统,从处理器执行主处理器的指令或者预定义任务,两个处理器是一种主从关系。文中CPU0是主处理器,控制系统和共享资源,CPU1是从处理器,OCM做CPU0和CPU1通信的共享内存。实现了启动Zynq的双核CPU,各自同时运行裸机程序,通过共享内存,实现了CPU之间的通信,并将运行信息在OLED上显示出来。
Multi-core processors mainly consists of two types,symmetrical multi-core processors(SMP) and asymmetric multi-core processors(AMP).At present most general multi-core processors are SMP which are equal among different CPUs,sharing the operating system,memory,peripherals and other resources.Most of AMP is the architecture adopted by the embedded multi-core processor,where a master CPU controls system operation and resources allocation,and the slave CPUs execute commands or predefined tasks from master CPU. Zynq is fully programmable chip launched by Xilinx recently,and is a processor with newarchitecture with ARMas its core and FPGA as its programmable peripheral.As an AMP,it includes two Cortex-A9 processors which can be configured to concurrently run independent software executables,in which a master processor controls the system,the slave processors execute the instruction or predefined tasks from the master processor,and it is a master-slave relationship between them.In this paper,CPU0 is treated as the master which conducts the system control and resources sharing,and CPU1 as the slave,and the on-chip memory(OCM) is used as shared memory for communication between CPU0 and CPU1.The startup of double-kernal CPU of Zynq is realized,and they run respective bare-metal program simultaneously.By sharing memory,the communication between CPUs is realized and the running information are displayed in the organic light-emitting diode(OLED).
出处
《计算机技术与发展》
2018年第3期60-62,66,共4页
Computer Technology and Development
基金
江苏省高校自然科学研究项目(14KJD520011)
关键词
Zynq
非对称多核芯片
共享内存
片上内存
主从关系
Zynq
asymmetric multiprocessing
shared memory
on-chip memory
master-slave relationship
