摘要
针对嵌入式GPU与主存之间进行数据交互时出现速度不匹配的问题,设计了一种适用于嵌入式GPU的二级高速缓存Cache控制器.二级Cache控制器采用四路组相联的映射结构,使用伪最近最少使用(Pseudo_LRU)替换算法,可以管理16~512kB的二级高速缓存.实验结果表明,当选取Cache大小为128kB时,Cache的命中率达到71.12%.
A suitable for embedded GPU cache controller is designed for the speed mismatch problems datainteraction between main memory and embedded GPU. The cache controller adopts a four-way set associativemapping structure, uses pseudo-Least Recently Used replacement algorithm. The size of CacheSRAM can beconfigured, which configuration range is 32-512 kB. The experimental results show that when the CacheSRAMcapacity is 128 kB, hit rate of the graphics applicatioffs Cache can reach to 71.12%, the cache controller can furtherenhance the overall performance of embedded GPU.
出处
《微电子学与计算机》
CSCD
北大核心
2018年第2期94-99,共6页
Microelectronics & Computer
基金
国家自然科学基金重点资助项目(61136002)
西安市科技发展计划资助项目(CXY1440(10))
