摘要
在含有FPGA的数字信号处理电路和控制电路中,为了实现将原始AD采样数据或中间处理结果数据的导出,供后续分析处理使用,从数据传输的稳定性、系统实现的简易性、价格低廉等角度出发,研究设计了基于FPGA TSE IP核的嵌入式百兆以太网数据传输系统。首先,详细分析了以NiosII CPU软核处理器为核心的以太网数传系统的SOPC各模块的硬件设计,主要包括以TES IP核为主的以太网MAC,采用乒乓缓存方式保证数据的连续不间断传输,以及通过接收客户端指令来控制数传的开始和暂停;然后,利用MicroC/OS-II嵌入式实时操作系统的多任务方式,基于Niche stack TCP/IP协议栈,完成了系统的软件设计,并给出了软件程序流程;最后,通过传输并接收特定的数据,验证了系统数据传输的速率和准确性。结果表明在传输速率达到51 Mbps时,系统稳定可靠。
In digital signal processing or control circuit based on FPGA,in order to export original sampling data or intermediate processing result data for analyzing and processing later,from the view of stabile transmission,easy realization and low cost,a 100 Mbps Embedded Ethernet data transmission system based on FPGA TSE IP core is designed.First,the paper introduces the hardware design thought in SOPC with the main processor NiosII CPU,mainly including the Ethernet MAC designing based on TSE IP core.Uninterrupted data transmission during all transmit time is guaranteed by Pingpang RAM mechanism and a method of controlling data start and stop transmitting is also designed.Then,using MicroC/OS-II real-time operating system of multi task mode,and based on Niche stack TCP/IP protocol,the software design of the system is realized.Also,the software program flow chart which details the software work flow of the system is given.Finally,by transferring desig-nated data,a verification method of rate and stability during data transmission is provided.The test result shows that the system is stable and reliable in data transmission when the rate is up to 51 Mbps.
出处
《液晶与显示》
CAS
CSCD
北大核心
2017年第8期607-613,共7页
Chinese Journal of Liquid Crystals and Displays
