摘要
提出了一种内置于SAR ADC的低功耗DAC,采用不同缩放类型分段组合的方式,明显减小了芯片占用面积,降低了功耗。基于华润上华公司的0.35μm CMOS工艺,利用Cadence Spectre仿真工具对电路进行分析,结果显示该DAC整体电路的功耗为0.93mW,最大积分非线性(INL)为-0.74LSB,最大微分非线性(DNL)为-0.48LSB,优值(FOM)为3.81,版图的面积为0.086mm^2,很好地满足了低功耗和小面积的要求。
A low power DAC built into SAR ADC was proposed,adopting the method of different scaling types of combination.The occupied area and power consumption were reduced significantly.The circuit was simulated with Cadence Spectre simulation tools in CSMC 0.35μm CMOS technology.The results showed that the power consumption of the whole circuit was 0.93 mW,the maximum INL（integral nonlinearity）and DNL（differential nonlinearity）were-0.74 LSB and-0.48 LSB,respectively,the FOM（figure of merit）was 3.81,and the occupied layout area was 0.086mm^2.This DAC could meet the requirements of SAR ADC for low power consumption and small area.
作者
蔡舟
张涛
CAI Zhou ZHANG Tao(School of Information Science, Wuhan University of Science and Technology, Wuhan 430081, P. R. China)
出处
《微电子学》
CAS
CSCD
北大核心
2016年第6期726-730,735,共6页
Microelectronics
基金
湖北省自然科学基金资助项目(2011CDB234)
湖北省教育厅科学技术研究计划重点项目(D20101104)
关键词
不同缩放
低功耗
分段组合
DAC
Different types of scaling
Low power
Piecewise combination
Digital to analog converter
