摘要
当前在高速数据系统中,LVDS接口已被广泛应用,为实现同系列设备之间的智能识别、自动握手以及LVDS高速数据链路通信质量的检测,利用FPGA的IO电路结构,设计一种模拟IIC总线协议电路,该IIC总线高效地实现设备之间的信息双向传递;同时利用FPGA内部丰富寄存器资源设计PRBS码型电路来检测LVDS接口芯片电路误码率;实际测试表明该多通道LVDS传输方式在2米长电缆连接能够实现数据的稳定、低误码率传输,并且在时钟频率为100 MHz时,数据传输速率高达4.68 Gb/s。
LVDS interface has been widely used in high speed data system.In order to realize the intelligent recognition,automatic handshake and the communication test of LVDS high speed data link,FPGA IO circuit is used to design a kind of IIC bus protocol.The IIC bus is used for information transmission between devices;meanwhile,taking advantage of FPGA internal register resources to design PRBS circuit which is used to detect the bit error rate of LVDS interface chip.The experiment shows that the multi-channel LVDS transmission can achieve data stability,low error rate transmission in two meters cable connection,the data transmission rate can reach up to 4.68Gb/s when the clock is 100 MHz.
出处
《计算机测量与控制》
2016年第7期181-182,186,共3页
Computer Measurement &Control
