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基于HEVC整数DST的VLSI设计与实现

VLSI Design of 2D DST Architecture for HEVC
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摘要 为了提高帧内编码性能,HEVC(High Efficiency Video Coding)首次应用整数离散正弦变换(The discrete cosine transform,DST)模式.针对现有DST算法运用到硬件设计中存在的设计电路面积较大、运算速度较慢的问题,结合DST矩阵系数运算数值的特点,提出了一种新的DST算法.并以此算法为核心,设计出了对应的专用有符号乘法器,通过采用单端口输入输出和组合累加器的方法,提高了电路的运算速度以及降低了电路的工作面积.在SMIC 0.18μm工艺下综合得到该电路最快工作频率为250MHz,电路面积为358 940μm2.从仿真结果来看,该设计的2D-DST电路有效,并能够获得较为精简的电路. To improve the Intar coding performance, HEVC( High Efficiency Video Coding) is applied to Integer discrete sine transform for the first time. To solve the problem of that the DST algorithm applied to hardware design that can increase circult area and reduce operational speed, a new DST algorithm is proposed based on the characteristics of the DST matrix coefficients. And the special signal multiplier is designed by the new algorithm. To increase operational speed and to reduce circuit area, the circuit adopts the single-port input and output and the combination accumlation method. Using SMIC 0. 18μm technology, the proposed architecture is implemented with the maximum work frequency at 250 MHz and 358 940 μm^2 circuit area. From simulation result, this design is working and can get a streamline circult.
出处 《微电子学与计算机》 CSCD 北大核心 2016年第3期20-24,共5页 Microelectronics & Computer
关键词 离散正弦变换 专用有符号数乘法器 运算速度 电路面积 DST special signal multiplier arithmetic speed circult area
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参考文献5

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