摘要
为了开发具有一定灵活性的高性能低功耗分组密码处理器,提出了一种粗粒度可重构阵列架构BCORE.在对分组密码算法进行分析的基础上,在阵列中集成了必要的功能单元和互连,并可以由称为动态部分可重构的配置控制机制在运行时进行配置.分别用非流水线和流水线方式在可重构阵列上映射了AES算法.在流水线方式时利用了动态部分可重构能力以提高性能.仿真和综合结果表明最高吞吐率接近2.5Gb/s,与其他平台的对比表明粗粒度可重构阵列在实现AES算法时平衡了性能、灵活性和实现效率.
For developing a block cipher processor with certain flexibility,high performance and power efficiency,a coarse-grained reconfigurable array architecture named BCORE is proposed.Based on the analysis of a set of block cipher algorithms,the necessary processing elements and interconnections are integrated into the array,which can be programmed at runtime by a control mechanism called dynamically partial reconfigurable.AES algorithm is mapped on the reconfigurable array by non pipeline and pipeline style separately. The dynamically partial reconfigurable ability is exploited for pipeline implementation in order to improve performance.Simulation and synthesis result shows that the maximum throughput achieved is nearly 2.5 Gb/s.Comparing with other platforms reveals that coarse-grained reconfigurable array makes a good balance between performance, flexibility and implementation efficiency.
出处
《微电子学与计算机》
CSCD
北大核心
2015年第9期1-5,共5页
Microelectronics & Computer
基金
科技部"八六三"重点项目子课题(2012AA011801)
关键词
粗粒度可重构阵列
动态部分可重构
算法映射
AES
coarse-grained reconfigurable array
dynamically partial reconfigurable
algorithm mapping
AES
