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一种基于FPGA的航空总线容错机制设计 被引量:2

A new avionics bus fault tolerance mechanism design based on FPGA
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摘要 航天应用中,单粒子翻转引发SRAM型FPGA的错误最多,而EDAC设计在纠错模块中有着广泛的应用。将依据扩展海明码设计的[40,32]EDAC模块嵌入到ARINC 659的双口数据DPRAM和指令SRAM中,提高了总线控制器的容错处理能力。 In the space environment, the most fault in SRAM type FPGA is the effect of single event upset (SEU). The EDAC module has a broad application in the field of aerospace error detection. In this paper, we use extension Hamming code to design [40,32] EDAC module and algorithm, which is embedded in ARINC 659 data dual port RAM and instructions SRAM module, to improve the fault tolerance ability of the ARINC 659 bus controller.
作者 丁志平
出处 《微型机与应用》 2015年第10期20-21,24,共3页 Microcomputer & Its Applications
关键词 ARINC 659 单粒子翻转 错误检测与纠正 海明码 ARINC 659 single event upset(SEU) error detection and correction(EDAC) Hamming code
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