摘要
虽然IEEE1149.1标准的提出及应用很好地解决了集成电路的测试问题,然而该标准在对被测电路进行实时故障诊断时却遇到了瓶颈。针对这一问题,利用并行特征分析器(PSA)及跟踪存储技术设计了一种基于IEEE1149.1标准的测试结构,结构中离线部分主要实现边界扫描基础测试并为在线测试提供控制信号,在线部分主要实现实时故障的诊断。设计采用Verilog语言建模,并用QuartusII软件仿真。仿真结果表明该设计能较好地检测出实时故障。
As the IEEE Std 1149.1 is proposed and applied,the problem of integrated circuit test（ICT） can be solved well.However,a bottleneck is encountered when the standard is employed to carry out the real-time fault diagnosis of the circuit under test（CUT）.Focused on this issue,taking advantage of the parallel signature analyzer（PSA） and the trace storage technology,an online test structure based on IEEE Std 1149.1 is designed.In the structure,off-line part of the principal is used to realize boundary scan-based testing and provide the control signals for the online test,the online part of the principal is used to realize real-time fault diagnosis.In the design,the Verilog language is used for modeling,while the Quartus Ⅱ software is used for simulation.The simulation results indicate that the design can detect the real-time failure better.
出处
《测控技术》
CSCD
2015年第1期55-58,共4页
Measurement & Control Technology
