摘要
为了便于数字信号处理器(DSP)的架构探索,提出了一种全新的基于Gem5模拟器Atomic模型,为顺序多发射、多级执行的DSP进行周期精度高效建模的通用方法。通过修改Atomic现有的三级流水线,添加一级新的流水线,达到了在Gem5中为DSP进行周期精度仿真的目的;通过硬件表格类的设计,改变Gem5指令集与处理器的耦合,达到了在Gem5中为DSP进行快速高效建模的目的。运行基准测试程序Dhrystone2的结果表明,该建模方法得到的周期信息与RTL硬件代码的仿真结果相同。而对代码的统计表明,该建模方法能提高代码的复用率和可维护性,使建模能快速响应设计,缩短DSP设计迭代周期。
To facilitate the architecture exploration of digital signal processor （ DSP）, this paper proposed a new general mod- eling method for inorder multi-issue, muhi-stage execution DSP based on Gem5 Atomic CPU model. This DSP modeling meth- od modified the original three-stage pipeline in Gem5 Atomic model and added a new pipeline stage to achieve the correctness of cycle-accurate modeling. This method also designed a new hardware table class and modified the coupling of ISA and CPU to gain the high efficiency. The result of running Dhrystone2.1 shows that this modeling method concludes a same result with the RTL code. Furthermore, statistics of the code indicates that the modeling method can promote the maintainability of the code. This method lets the modeling do quick response to the design and shorten the DSP design cycle.
出处
《计算机应用研究》
CSCD
北大核心
2015年第1期121-124,共4页
Application Research of Computers
基金
"核高基"科技重大专项资助项目(2012ZX01034001-002)
关键词
Gem5模拟器
周期精度
高效建模
架构探索
处理器建模
Gem5 simulator
cycle-accurate
high-efficient modeling
architecture exploration
DSP modeling
