摘要
针对目前常用位同步时钟恢复电路即超前-滞后型锁相环和1位同步器两种方法的不足之处,提出了一种使用DDS原理实现的快速时钟恢复方案。该方案采用DDS技术作为高精度任意分频单元,并在此基础上结合两种方法的优点,完成了位同步时钟恢复的改进设计。该方法适用频率范围宽,同步速度快,同步精度高,能够有效地降低频差的影响。给出了方案设计原理及实现方法,使用FPGA完成设计并对其性能做了分析及仿真、测试。
To the shortcomings of two clock recovery circuit, lead-lag digital PLL and 1 bit synchronizer, a new method of fast clock rec, overy scheme using the DDS principle is implemented. The project adopts DDS technology as the high precision arbi- trary frequency unit, and on this basis, the improved design of bit synchronization clock extraction is completed, which can fast ex- tract clock from the data stream in real-time. The design principle and implementation method are given, and it is implemented with FPGA. Analysis and simulation test on its performance are given at last.
出处
《电子技术应用》
北大核心
2014年第8期51-53,61,共4页
Application of Electronic Technique
