摘要
分析了应用于DRFM系统的4bit相位ADC原理并介绍了一种4bit相位ADC电路结构,该电路采用类似于幅度ADC的Flash拓扑在标准半导体工艺下设计并实现,芯片面积2.3mm×1.7mm,功耗620mW,数字输出满足LVDS电平标准。测试结果显示该ADC瞬时带宽高于1GHz,动态范围大于26dB。
The principle of 4 bit phase digitizing novel circuit structure of it is proposed. The circuit chitecture and is implemented by standard semicond ADC for DRFM is ana employs the structure uctor technology. Wit lyzed. Furthermore, a similar to the flash ar- h the chip area of 2.3mm × 1.7 mm and the power consumption of 620 mW, all the digital output interface is designed to obey standard LVDS transmission mode. Test results show that the IBW of ADC is higher than 1GHz and its dynamic range is wider than 26 dB.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2014年第3期206-210,共5页
Research & Progress of SSE
关键词
模数转换器
相位量化
数字射频存储器
瞬时带宽
analog-to-digital converter（ADC）
phase digitizing
digital radio frequency memory（DRFM）
instantaneous bandwidth（IBW）
