摘要
为使DRM／DAB／AM／FM频率综合器具有良好性能，本文设计了一种高速大分频比低功耗吞吐脉冲分频器．此吞吐脉冲分频器由32／33双模预分频器（dual—modulus prescaler，DMP）、5位吞吐计数器和11位可编程分频器及时序控制电路构成．此吞吐脉冲分频器内部的不同模块分别采用SCL、TSPC、CMOS静态触发器及可置位的CMOS静态触发器等多种触发器结构优化，使此吞吐脉冲分频器具有高速、大分频比和低功耗的特点．此吞吐脉冲分频器应用中芯国际SMIC0．18μm RFCMOS工艺流片，芯片核心面积为270μm×110μm．测试结果显示，在1．8V工作电压的条件下，此吞吐脉冲分频器的最高工作频率为3．4GHz，工作频率范围为0．9—3．4GHz．在输入信号频率为3．4GHz，分频比为45695时，功耗为3．2mW．实验结果表明，此吞吐脉冲分频器完全满足DRM／DAB／AM／FM频率综合器的要求．
For the good performance of DRM/DAB/AM/FM frequency synthesizer, the implementation of a high-speed large division ratio low-power pulse swallow frequency divider is described, which consists of a divided-by-32/33 dual-modulus prescaler （DMP）, a 5 bits swallow counter, an 11-bits programmable divider, and a time sequence control circuit. The different modules of pulse swallow frequency divider apply SCL, TSPC, CMOS static flip-flop DFF, and CMOS static flip-flop DFF with preset to realize the low power, large division ratio, and high speed performances. The chip has been fabricated in a 0. 18 μm CMOS process of SMIC and the core area is 270 μm×110μm. Measured results show that its most high operation frequency is 3.4 GHz and the rang of operation frequency is from 0. 9 GHz to 3.4 GHz. And when the operating frequency is 3.4 GHz and division ratio is 45 695, the maximum core power consumption is 3.2 mW under 1.8 V power supply. Its performance satisfies the requirement of DRM/DAB/AM/FM frequency synthesizer.
出处
《哈尔滨工业大学学报》
EI
CAS
CSCD
北大核心
2014年第3期74-79,共6页
Journal of Harbin Institute of Technology
基金
科技部中小企业创新基金资助项目(11c26213211234)
内蒙古自治区高等学校科学技术研究资助项目(NJZY11016)
关键词
吞吐脉冲分频器
高速
大分频比
低功耗
DRM
DAB
AM
FM频率综合器
pulse swallow frequency divider
high speed
large division ratio
low power consumption
DRM/DAB/AM/FM frequency synthesizer
