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DAB射频接收机中的高性能电荷泵设计

Design of high performance charge pump for DAB RF tuner
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摘要 实现了一种用于DAB数字广播射频接收机的改进型电荷泵电路.电路核心部分采用带有运算放大器的改进型的共源共栅极电流镜结构实现,以改善电荷泵的电流匹配度.电荷泵中的带隙基准源采用自偏置宽摆幅电流镜结构以增加输出电压的范围.电荷泵中的运算放大器采用叠式共源共栅极结构以获得更大的输入共模范围与更高的增益.芯片采用0.18μm CMOS工艺实现.测试结果显示,电荷泵的电流为0.3 mA.电流失配率在0.3~1.6 V输出电压范围内小于1%.在1.8 V供电电压下,芯片功耗约为4 mW.实验结果显示,所设计的电路结构实现了充放电电流的匹配,且功耗较低. A type of improved charge pump for digital audio broadcasting(DAB) radio frequency(RF) tuner is realized.An improved cascode current mirror with operational amplifier is used to enable the charge pump current to be well matched in the core part of the proposed circuit.The self-biasing wide-swing current mirror is adopted in the band-gap of the proposed charge pump to offer a wider range output voltage.The folded operational amplifier in the circuit is realized with folded cascode topology for wider common-mode input range and higher gain.The chip is realized in 0.18 μm complementary metal oxide semiconductor(CMOS) process.Measurement results show that the charge pump current is 0.3 mA.The measured current mismatching can be less than 1% in the output voltage range of 0.3 to 1.6 V.The power consumption is 4 mW under a 1.8 V supply voltage.The experimental results show that the proposed topology structure has realized the match of the charge and discharge current and the lower power consumption.
出处 《东南大学学报(自然科学版)》 EI CAS CSCD 北大核心 2012年第6期1047-1051,共5页 Journal of Southeast University:Natural Science Edition
基金 国家自然科学基金资助项目(61106024 61201176) 教育部高等学校博士学科点专项科研基金资助项目(20090092120012) 东南大学科技研究计划资助项目(KJ2010402)
关键词 电荷泵 锁相环 电流失配 运算放大器 charge pump phase-locked loop current mismatch operational amplifier
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  • 1周建政,王志功,李莉,王科平,贾鹏.数字调幅广播发展的技术瓶颈与解决方案[J].广播与电视技术,2007,34(2):108-111. 被引量:6
  • 2Lee J, Kim S, Kim J, et al. 159.2 mW SoC implementation of T-DMB receiver including stacked. Proceedings of Custom Inte- grated Circuits Conference, 2008:679. 被引量:1
  • 3Liou J J, Krstic A, Jiang Y M, et al. Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices.IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2003, 22(6): 756. 被引量:1
  • 4Staszewski R B, Muhammad K, Leipold D, et al. All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS. IEEE J Solid-State Circuits, 2004, 39(12): 2278. 被引量:1
  • 5Obote S, Syoubu K, Fukui Y, et al. A novel (N + 1/2) pulse swallow programmable divider for the prescaler PLL frequency synthesizer. Analog Integrated Circuits and Signal Processing, 1999, 21(2): 117. 被引量:1
  • 6Lo C W, Luong H C. A 1.5-V 900-MHz monolithic CMOS fast- switching frequency synthesizer for wireless applications. IEEE J Solid-State Circuits, 2002, 37(4): 457. 被引量:1
  • 7Van Paemel M. Analysis of a charge-pump PLL: a new model. IEEE Trans Commun, 1994, 42(7): 2490. 被引量:1
  • 8Sumi Y, Obote S, Kitai N, et al. PLL synthesizer with multiprogrammable divider. IEEE Trans Consumer Electron, 1999, 45(3): 950. 被引量:1
  • 9Yang C Y, Dehng G K, Hsu J M, et al. New dynamic flip-flops for high-speed dual-modulus prescaler. IEEE J Solid-State Circuits, 1998, 33(10): 1568. 被引量:1
  • 10Soares N J, van Noije W A M. A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC). IEEE J Solid-State Circuits, 1999, 34(1): 97. 被引量:1

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