摘要
实现高精度时差估计(TDOA)需要监测接收机中的授时系统提供含精确时间戳信息的实时快照数据。针对上述问题,提出了一种基于DDR2高速缓存技术的可变速率的时域数据采集系统。该系统以现场可编程门阵列(FPGA)为核心,配备了两组独立DDR2存储器对数据高速缓存,并巧妙利用了双FIFO的乒乓缓存结构,以及互斥片选结构。经过测试,系统能够实时采集1kHz到20MHz十七种可变带宽的时域数据,并通过以太网口回传给计算机分析并估计出信号到达不同接收机的时差。
In order to calculate the high-precision time difference of arrival（TDOA）,the time synchronization system in the monitoring receiver should provide reliable snapshot data with time stamp.This paper designs and realizes a variable speed time-domain data acquisition system based on DDR2 memory caching technology.The system uses FPGA as its core and employs two groups of high-capacity DDR2 for high-speed caching.With the dual FIFO Ping-Pong caching technology and the structure of exclusive accessing and chip selecting,this system can acquire and storage real-time data with seventeen kinds of variable bandwidth from 1 kHz to 20 MHz,then send these data to computer for analyzing via LAN and calculating the time difference of arrival to different receivers.
出处
《雷达科学与技术》
2013年第5期522-526,共5页
Radar Science and Technology
关键词
快照数据
现场可编程门阵列
精确授时系统
可变数据率
乒乓操作
snapshot data
field programmable gate array（FPGA）
high-precision timing system
variable-speed
Ping-Pong operation
