摘要
介绍了一种非二进制权重的高能效比逐次比较型模数转换器。该ADC采用了非二进制权重的电容结构以降低工艺失配对性能的影响,极大地减小了总电容的值;使用了自适应时钟来实现每一位的量化,提高了采样频率,并且不需要外界提供高速时钟;采用了注入扰动的最小均方校准算法,用很小的电路代价实现了后台数字校准。本芯片在SMIC 0.13μm工艺上实现,芯片模拟部分核心面积为0.042mm2,数字校准模块面积为0.04mm2,芯片工作在25MHz采样率时功耗为2.8mW,信噪失真比为58.6dB,有效位数为9.5位。
A non-binary high power-efficiency SAR ADC is presented. Non-binary welgntea capacitive array is used to reduce the influence on performance caused by mismatch, thus small total capacitance is possible; a self-timing clock is used to realize quantization of each bit to im- prove sample rate and make high frequency synthesizer dispensable; the least mean square algo- rithm with dither signal is used to realize background digital calibration with little cost. This chip is implemented in SMIC 0. 13μm CMOS technology. Analog core of this SAR ADC occupies 0.042 mm2 , digital calibration module occupies 0.04 mm2. It consumes 2.8 mW when operating at 25 MHz. SNDR is 58.6 dB getting 9.5 bit ENOB.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
2013年第4期382-388,共7页
Research & Progress of SSE
