摘要
设计了一种基于混合编码DAC的低功耗SAR ADC.其分段电容DAC采用混合编码,减小了短时脉冲波形干扰的影响;为降低DAC寄生效应和电容阵列失配误差的影响,在DAC和比较器的版图设计中考虑了一些匹配技术.采用GF(Global Foundry)0.35μm CMOS工艺流片验证,该ADC在500KSPS的速度下其INL在-0.6～0.4LSB区间范围内,DNL在-0.2～0.7LSB区间范围内,SNDR为54.13dB,有效位为8.7位.整个电路的功耗为537.9μW.
A low-power successive approximation register analog-to-digital converter with hybrid encoding DAC is proposed in this paper.To decrease the glitch of the charge redistributed DAC,the split-capacitor DAC adopt the hybrid code.To increase the matching accuracy and reduce the influence of parasitic effect of DAC,some matching techniques are adopted in the layout design of the proposed DAC and capacitor.The SAR ADC is fabricated and verified in GF（Global Foundry）0.35μm CMOS process.The measurement results have shown that at 500KSPS,the INL and DNL are-0.6～0.4LSB and-0.2～0.7LSB,respectively,the SNDR is 54.13dB and the ENOB is 8.7bits.The total circuit consumption is 537.9μW.
出处
《微电子学与计算机》
CSCD
北大核心
2013年第7期91-94,共4页
Microelectronics & Computer
基金
国家科技重大专项(2012ZX03004008)
